Cray

PHYTEC provides the L0 Controller Module for use as a service processor in the Cray XT3, a third generation massively parallel processor (MPP) supercomputer. A custom subassembly derived from the phyCORE-SC520, the L0 generates routing tables and monitors the health of the components on its host board. The L0 runs embedded ELinOS and interfaces through the GP bus to an FPGA on the host circuitry, which has additional devices to extend the functionality of the L0 module. In addition to this cabinet-level safety and control implementation, a second application uses the PCI bus on the L0 module, as well as two additional network interfaces to turn the L0 into a network router.

Building on the success of its predecessors, the Cray T3D and the Cray T3E systems, the Cray XT3 system brings astounding new levels of scalability and sustained application performance to high performance computing (HPC). Purpose-built to meet the special needs of capability class HPC applications, each feature and function is designed for larger problems, faster solutions, and a greater return on investment.